Summary

The provided content highlights a cluster of research efforts focusing on hybrid cryptographic implementations for AArch64 architectures. Early works by Hanno Becker and his team developed efficient scalar-vector implementations for Keccak and SPHINCS functions on this platform, while other authors explored faster algorithms in NTT rings. Notably, the IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES) have featured multiple papers addressing faster cryptographic operations, specifically dilithium, kyber, and sabor, alongside optimizations for specific hardware cores like the Cortex-M4 and Apple M1. Research groups in ACNS, PQCrypto, and TCHES have contributed to verifying signatures in small memory units, reducing the size of RAM required for these high-security schemes. A significant portion of the literature emphasizes reducing implementation complexity and computational overhead through hybrid scalarvector techniques, which aim to balance performance with the security demands of Next-Generation Cryptography. These advancements represent ongoing work aimed at making standard cryptographic functions more efficient and robust, ultimately contributing to the broader goal of accelerating the transition to post-quantum security standards.

Title

Matthias J. Kannwischer

Description

Matthias J. Kannwischer

Keywords

slides, taiwan, cortex, cryptography, code, paper, university, taipei, quantum, transactions, systems, talk, security, post, hardware, implementations, yang

NS Lookup

A 188.40.30.120

Dates

Created 2026-04-12

Updated 2026-04-12

Summarized 2026-04-17